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Communication Protocol - I2C

I2C (Inter-Integrated Circuit) is a serial communication bus that allows for multiple hosts to exist, but only one host can be online at a time. I2C consists of two open-drain signal lines, making the wiring simple. It utilizes pull-up resistors, with typical voltage levels of 3.3V or 5V for positive logic. The transmission speed is divided into fast mode (400Kb/s), standard mode (100Kb/s), and low-speed mode (10Kb/s).

On the I2C bus, the slave is selected by its I2C address. This allows multiple slaves to be controlled by a single host using two lines.

I2C Pins

  • SCL (serial clock): A square wave generated by the host to control the transmission rate and latch the data.
  • SDA (serial data): This is a half-duplex, synchronous signal line used to transmit data, including addresses, control signals, and communication data.

I2C Address

  • The I2C address is divided into a 7-bit address and a 1-bit read/write indicator.
  • Each device on the I2C bus must have a unique address to avoid conflicts. Some devices allow the I2C address to be programmatically set.

I2C Communication

  • START: The host initiates the communication by pulling SDA low while SCL is high.
  • STOP: The host terminates the communication by releasing SDA (raising it to a high level) while SCL is high.
  • ACK (acknowledge): During I2C transmission, each byte (8 bits) is transferred with each SCL pulse. The 9th pulse is reserved for the slave's acknowledgment, and each ACK signal indicates the success of the previous transmission.

Example of an I2C Transmission Segment

The transmitted value in this segment is 11001101:

  1. The host pulls SDA low to generate the START signal.
  2. The first bit is set, and the host pulls SCL low to output the clock signal through the DAC.
  3. When it reaches the 9th bit, the host does not pull SDA low. If the slave confirms the complete transmission, it pulls SDA low to inform the host.

Valid Data Transmission

  1. During the high level of SCL (data transmission), SDA must remain stable to be valid.
  2. SDA can only change its value during the low level between SCL pulses.
  3. When SCL is high and SDA changes, it is interpreted as a START, RESTART, or STOP event.

Rise/Fall Time in Interface Circuit

As shown in the diagram, the transistor conducts when the signal is at a low level and discharges the capacitance \(C_b\) to a low level. Conversely, the transistor turns off when the signal is at a high level, and the pull-up resistor charges \(C_b\) to a high level.

  • \(t_r\) (rise time): The maximum time for the signal to transition from a low level to a high level. Since I2C is an open-drain signal, the rise time is determined by the RC time constant of the pull-up resistor and the bus capacitance.
  • \(t_f\) (fall time): The maximum time for the signal to transition from a high level to a low level.

Calculation of I2C Pull-Up Resistor

  • Minimum value of pull-up resistor: \(R_{Pull(Min)}=\frac{V_{DD}-V_{OLMAX}}{I_{SinkMax}}\)
  • Maximum value of pull-up resistor: \(R_{Pull(Max)}=\frac{t_r}{0.8473*C_b}\)

The minimum value of the pull-up resistor results in the shortest rise time. If a resistor with a smaller value is used, it will cause excessive current consumption when the output transistor is turned on (logic low level), violating the specification for maximum logic low level output.

The maximum value of the pull-up resistor will result in the longest rise time. If a pull-up resistor greater than this value is used, it will violate the timing requirements.

\(V_{DD}\) represents the supply voltage; \(V_{OLMAX}\) represents the maximum logic low level (typical value is 0.4V); \(I_{SinkMax}\) represents the maximum sinking current (typical value is 3mA); \(C_b\) represents the bus capacitance, which depends on the length and width of the PCB traces and the capacitance of the devices connected to the bus.

Calculation example:

References and Acknowledgements

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